0000002603 18S 2SWS SE B.Sc./M.Sc. Seminar: Future Trends in High Performance Computing (IN2183,IN2107,IN0014)   Hilfe Logo

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B.Sc./M.Sc. Seminar: Future Trends in High Performance Computing (IN2183,IN2107,IN0014) 
Sommersemester 2018
Informatik 5 - Lehrstuhl für Wissenschaftliches Rechnen (Prof. Bungartz)
Angaben zur Abhaltung
In the last ten years the period of vast increases in processing power mostly achieved by increasing the clock frequency of a processor has come to an end. Instead, computer architectures are getting more complex in order to accommodate the growing demand for processing power. Modern CPUs typically have a wide range of SIMD instructions for fine-grained data parallelism, and are capable of executing several threads on each of their several cores. Memory accesses are passed through multiple cache levels to hide memory access latencies. In addition to that, hardware specialized in performing massively parallel computations is getting more and more popular. Examples are GPUs and accelerators such as the Xeon Phi. In the HPC context, several nodes, each with its own CPU(s) and GPU(s) may be joined into a cluster.

Regular programming techniques and paradigms are no longer sufficient to fully utilize this hardware. Frameworks such as OpenCL take the structure and heterogeneity of the underlying hardware into account and provide the programming environment to expose all available resources, such as GPUs and accelerators. The behavior of the hardware at runtime also needs to be considered. Modern Cluster architectures are not necessarily capable to run at peak utilization 100% of the time. To avoid the overheating of the hardware and the resulting degradation of the silicon, the clock frequency of the CPU may be drastically reduced, or single nodes may even be shut down completely for a time. In this seminar, we will explore these issues, along with software solutions that try to alleviate these measures by automatic distribution of tasks, automatic tuning to the target platform or by performing an automatic offloading of work to accelerator devices.

Preliminary List of Topics:

- MIC architectures (Intel Xeon Phi)
- Heterogeneous Computing
- Dark Silicon
- Energy Aware Computing Techniques in HPC
- Fault Tolerance
- Resource Aware Computing Concepts
- Beyond MPI: New Runtime Systems for HPC
- Mixed-Precision hardware acceleration for HPC
- DSLs for HPC (ExaStencils)
- MPI at Exascale
- Modeling vs. Automatic Tuning in HPC
- Exotic Hardware Architectures (e.g. Sunway TaihuLight)
- FPGAs in HPC

- Independent literature research
- Paper: Total 6-10 pages (max 10 pages). IEEE format double-column (Link to LaTeX template on Course Website)
- Presentation: 30 minutes talk + 15 minutes discussion

Mandatory attendance: Participants must attend all presentations. Absence may be approved for "good" reasons with a prior discussion to the supervisors. For absence due to sickness, a doctor's attest must be provided. Unapproved absence will result in grade deduction or failure.
Für die Anmeldung zur Teilnahme müssen Sie sich in TUMonline als Studierende*r identifizieren.
Anmerkung: Via Matching System
We encourage independent research and review of the available literature.
Weitere Informationen
The seminar will (partly) discuss research executed in the collaborative research unit Invasive Computing funded by the German Research Foundation (DFG).