849959067 21S 4SWS PR EI0463 Laboratory Course VHDL   Hilfe Logo

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EI0463 Laboratory Course VHDL 
practical training
Summer semester 2021
... alle LV-Personen
Chair of Integrated Systems (Prof. Herkersdorf)
(Contact information)
Allocations: 1 
Angaben zur Abhaltung
Subject of this lab course is the design of digital ICs using the hardware description language VHDL. The lab covers modeling and simulation of digital circuits as well as their synthesis into gate level netlists.
The main aspects to be conveyed are:
- Composition of VHDL models (Entity, Architecture, Package)
- Concurrency of hardware and its representation in VHDL
- Structural and behavioral modeling
- Processes as interface between parallel and sequential modeling
- Time modeling in VHDL (event queue, delta cycles)
- Synchronous design
- Synthesizeability of models
The exercises to be completed by the participants are taken from a data communications application. State-of-the art industrial tools are being used.
Boolean Logic, Basics of digital circuit design.
Basic concepts of modeling Hardware
Simulation and Synthesis of VHDL Models
Basic ability to develop own synthesizable HW models
calculation exercises
At the beginning of the course, the theoretical basics will be presented in severel introductory lectures. The exercises will be done independently by the participants, based on the given lab manual. There is no fix schedule, the exercises can be carried out with arbitrary timing. In addition, tutor hours are offered where an experienced student is offering assistance to solve the exercise problems.
Register at TUMonline from 16th March to 16th April 2021
Für die Anmeldung zur Teilnahme müssen Sie sich in TUMonline als Studierende*r identifizieren.
Z. Navabi; "VHDL - Analysis and Modeling of Digital Systems", McGraw-Hill ;
P. Ashenden, "The designer´s Guide to VHDL", Morgan Kaufmann;
J. Reichardt, B. Schwarz, "VHDL-Synthese", Oldenbourg
Online information
e-learning course (moodle)
Additional information
additional information